The invention relates to a photo detector device and an integrated circuit (“IC”) comprising one or more photo detector devices according to the invention.
Photo detectors are devices that convert optical signals into electrical signals. Photo detector devices are for example employed to detect light for the purpose of optical communication.
Nowadays, optical technology is focusing on photonic integrated circuits on a chip. Indium-gallium-arsenide (“InGaAs”) photo detectors are not easy to implement on a silicon chip, since lattice constants are different and InGaAs is a III-V compound semi-conductor. In general, the elements Indium, Gallium and Arsenide are all dopants in silicon to show donor or acceptor characteristics and could thus alter the silicon circuit performance if diffused.
Optical Input/Outputs (“IOs”) or optical chip-to-chip communication directly onto the chip is restricted today by the fact that the realization of optical detectors in Complementary Metal-Oxide Semiconductor (“CMOS”) integrated circuits is very challenging. Several approaches are found in the literature to integrate optical detectors into a commercial IC process. They range from on chip photo diodes (“PD”) implemented with PN junction available in the process over deep trench memory cells used as detector to hybrid implementations where additional semiconductor layers e.g. Germanium, may be placed on top of the chip.
Silicon is a usable semiconductor only for very short wavelength detectors. A CMOS process or even better a Bipolar Complementary Metal-Oxide Semiconductor (“BICMOS”) process offers a whole range of PN-junctions which may be used as detectors. However, in a state of the art process the doping levels are very high. As a result, the depletion width of such PN-junctions is very narrow, approximately 50 nm to 100 nm. This leads to very high junction capacitances, which severely limits the frequency response of such a detector, and it will result in a very small responsivity due to the small volume which may be used to absorb photons. The photo-current that is generated by incident light is limited by the charge mobility and thus limits the switching frequency of an optical detector. The faster the generated electrons are, the faster the optical detector becomes.
Using deep trenches as optical detectors has the benefit that depletion width and absorption length are decoupled. The depletion width forms horizontally on the sidewalls of the trenches and, since the light is usually applied normal to the chip surface, the absorption is perpendicular to the wafer surface. Deep trenches are in the order of 10 um deep, which is very much compatible with the absorption length in silicon (15 um) from light with a wavelength of 850 nm. However, these deep trenches were originally designed to form capacitors for embedded DRAM. As a result they show a very large amount of capacitance for a practical detector area. Using low doped silicon wafers and additional trenches to contact the low doped substrate, a high performance detector may be built. However, this requires a process modification, which will increase cost and decrease yield. Depending on the process this modification will also change the FET characteristics, which is highly undesirable.
Implementing an optical detector using a silicon on insulator (“SOI”) process is even more challenging. In such a process the bulk silicon only serves as a mechanical substrate and has no electrical function. The active silicon layer is only approximately 70 nm thick and the corresponding resistance is quite high. Generally, strained silicon techniques like “dual stress liner” or “embedded silicon germanium” are used to improve the switching characteristic of P-MOS and N-MOS transistors by introducing tensile or compressive stress on the atomic structure. Under certain circumstances, this principle may also be used to enhance the performance of optical detectors.
Another approach which would work for bulk and SOI processes, is to add additional semiconductor layers onto the already very complicated CMOS layer stack to form a detector. Using this approach, high performance detectors have been shown to be feasible. However, this approach is very undesirable for reasons of cost and yield. Strained Silicon is available for standard SOI processes and hence no process modification is required.